(1) Field of the Invention
The present invention relates to input/output circuit devices, and more particularly relates to input/output circuit devices connected to semiconductor devices supplied with a higher power supply voltage than a predetermined operating voltage (design voltage).
(2) Description of Related Art
In recent years, with a sharp reduction in the size of complementary metal-oxide-semiconductor (CMOS) devices, the power supply voltage supplied to the CMOS device has been decreasing from 5 volts to 3.3 volts.
However, a plurality of electronic makers will never change the operating voltages of semiconductor devices from 5 volts to 3.3 volts in unison. It is impossible to change the operating voltages of all semiconductor devices to be connected to other semiconductor devices. Therefore, very large scale integrated circuit (VLSI) devices designed, for example, under the assumption that their operating voltage is 3.3 volts need to interface (make connection) with other semiconductor devices operating at a known operating voltage of 5 volts.
In order to interface between a semiconductor device designed to have an operating voltage of 3.3 volts and a semiconductor device designed to have an operating voltage of 5 volts, an input/output circuit or device for avoiding the adverse effect produced by the potential difference between the operating voltages is required. In other words, a further high-breakdown-voltage input/output circuit that can absorb the potential difference between the operating voltages is required, resulting in an increase in cost.
An input/output circuit device according to a known example will be described hereinafter with reference to FIG. 7. As illustrated in FIG. 7, a known input/output circuit device is composed of two cascaded n-type MOS transistors, a pull-down transistor Q1 and a cascade transistor Q2.
The gate of the pull-down transistor Q1 is connected to a signal terminal Vn to which a ground voltage Vss (=0 volt) or a power supply voltage VDD (=3.3 volts) is fed, the source thereof is grounded, and the drain thereof is connected to an internal node Vc. The gate of the cascade transistor Q2 is applied with a power supply voltage VDD, one of a source and a drain thereof is connected to the internal node Vc, and the other thereof is connected to an input/output terminal V0 applied with a voltage of 0 volt or 5 volts. The substrate potential of each of the pull-down transistor Q1 and the cascade transistor Q2 is grounded.
The pull-down transistor Q1 and the cascade transistor Q2 both usually represent transistors designed to operate at a drain-to-source voltage of 3.3 volts or less. However, in this known example, the transistors Q1 and Q2 are cascaded to each other so that the voltage applied to the input/output terminal V0, i.e., 5 volts, is divided by the transistors Q1 and Q2. This allows the application of a voltage of 5 volts to the input/output circuit device.
However, the known input/output circuit device causes the following problems when a voltage of 5 volts fed from the input/output terminal V0 is divided by the pull-down transistor Q1 and the cascade transistor Q2. In other words, when the source-to-drain voltages of the transistors Q1 and Q2 are equal to each other, the potential of the internal node Vc is approximately 2.5 volts. Therefore, the source voltage of the cascade transistor Q2 is approximately 2.5 volts. This allows the application of a substrate bias voltage, i.e., a substrate-to-source voltage of approximately 2.5 volts. As a result, the hot-carrier tolerance of the pull-down transistor Q2 is reduced, resulting in a significantly reduced reliability life of the input/output circuit device.
In order to reduce the substrate bias effect, the voltage applied from the input/output terminal V0 needs to be divided between the transistors to reduce the potential of the internal node Vc. In this case, the potential difference between the source and the drain of the cascade transistor Q2 (between the internal node Vc and the input/output terminal V0) increases, also resulting in a significant reduction in the hot-carrier tolerance.